library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity UART_IN is
	PORT (	
	clk : in STD_LOGIC;
	ADDR_IN : in STD_LOGIC_VECTOR(0 downto 0); -- From op1 (0), or op2(1)
	
	-- Input from UART module
	UART_IN1 : in STD_LOGIC_VECTOR(31 downto 0);
	UART_IN2 : in STD_LOGIC_VECTOR(31 downto 0);
	
	DATA_OUT : out STD_LOGIC_VECTOR(31 downto 0)
	
	);
	
end UART_IN;

architecture Behavioral of UART_IN is
begin
	
	process(clk)
	begin
		if (clk'event and clk = '1') then
			if (ADDR_IN = "0") then
				DATA_OUT <= UART_IN1;
			else
				DATA_OUT <= UART_IN2;
			end if;
		end if;
	end process;

end Behavioral;

